A trench gate structure is generally known as a structure effective for refinement of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field-Effect Transistor).
FIG. 7 is a schematic sectional view showing the structure of a conventional semiconductor device having a trench gate type VDMOSFET.
The semiconductor device 100 includes an N+-type substrate 101. An N−-type epitaxial layer 102 is laminated on the N+-type substrate 101. A base layer portion of the N−-type epitaxial layer 102 forms an N−-type region 103, while a P-type body region 104 is formed on a surface layer portion of the N−-type epitaxial layer 102 vertically adjacently to the N−-type region 103.
A trench 105 is dug in the N−-type epitaxial layer 102 from a surface thereof. The trench 105 penetrates through the P-type body region 104, so that a deepest portion thereof reaches the N−-type region 103. A gate electrode 107 made of polysilicon doped with an N-type impurity in a high concentration is embedded in the trench 105 through a gate insulating film 106 made of SiO2 (silicon oxide).
An N+-type source region 108 is formed on a surface layer portion of the P-type body region 104 along the trench 105. A P+-type contact region 109 is formed at the center of the N+-type source region 108 in plan view, to penetrate through the N+-type source region 108.
An interlayer dielectric film 110 is laminated on the N−-type epitaxial layer 102. A source wire 111 is formed on the interlayer dielectric film 110. This source wire 111 is grounded. The source wire 111 is in contact (electrically connected) with the N+-type source region 108 and the P+-type contact region 109 through a contact hole 112 formed in the interlayer dielectric film 110. A gate wire 113 is electrically connected to the gate electrode 107 through another contact hole (not shown) formed in the interlayer dielectric film 110.
A drain electrode 114 is formed on a back surface of the N+-type substrate 101.
When the potential of the gate electrode 107 is controlled while applying a positive voltage of a proper level to the drain electrode 114, a channel is formed in the vicinity of an interface between the P-type body region 104 and the gate insulating film 106, and a current flows between the N+-type source region 108 and the drain electrode 114. Thus, a switching operation of the VDMOSFET is achieved.
For example, the product Ron·Qg of the on-resistance Ron and the gate charge quantity Qg is employed as an index indicating the switching performance of the VDMOSFET.
The on-resistance Ron is the resistance between a source and a drain. In the semiconductor device 100 shown in FIG. 7, the on-resistance Ron corresponds to the resistance between the N+-type source region 108 and the N+-type substrate 101 (between the source wire 111 and the drain electrode 114).
The gate charge quantity Qg corresponds to the quantity of charges stored in a combined capacitance of the gate-to-drain capacitance Cgd and a gate-to-source capacitance Cgs. In the semiconductor device 100 shown in FIG. 7, the gate-to-drain capacitance Cgd corresponds to a combined capacitance of the capacitance of a portion of the gate insulating film 106 sandwiched between the gate electrode 107 and the bottom surface of the trench 105 and the capacitance of a depletion layer 115 spreading from the interface between the N−-type region 103 and the P-type body region 104. In the semiconductor device 100 shown in FIG. 7, a gate-to-source capacitance Cgs corresponds to the capacitance of a portion of the gate insulating film 106 sandwiched between the gate electrode 107 and the N+-type source region 108.
The speed of the switching operation can be increased as the product Ron·Qg of the on-resistance Ron and the gate charge quantity Qg is reduced. As shown in FIG. 8, however, the on-resistance Ron and the gate charge quantity Qg are in the so-called trade-off relation, such that the former is increased when the latter is reduced and vice versa. In order to reduce the product Ron·Qg, therefore, one of the on-resistance Ron and the gate charge quantity Qg must be reduced, while increase of the other must be prevented.
FIG. 9 is a schematic sectional view showing the structure of another conventional semiconductor device having a trench gate type VDMOSFET.
The semiconductor device 401 includes an N+-type substrate 402. An N−-type epitaxial layer 403 is laminated on the N+-type substrate 402. A base layer portion of the N−-type epitaxial layer 403 forms an N−-type region 404, while a P-type body region 405 is formed on a surface layer portion of the N−-type epitaxial layer 403 vertically adjacently to the N−-type region 404.
A trench 406 is dug in the N−-type epitaxial layer 403 from a surface thereof. The trench 406 penetrates through the P-type body region 405, so that a deepest portion thereof reaches the N−-type region 404. A gate electrode 408 made of polysilicon (doped polysilicon) doped with an N-type impurity in a high concentration is embedded in the trench 406 through a gate insulating film 407.
An N+-type source region 409 is formed on a surface layer portion of the P-type body region 405 along the trench 406. A P+-type source contact region 410 is formed on the N+-type source region 409, to penetrate through the N+-type source region 409.
A drain electrode 415 is formed on a back surface of the N+-type substrate 402.
When the potential of the gate electrode 408 is controlled while grounding the N+-type source region 409 and applying a positive voltage of a proper level to the drain electrode 415, a channel is formed in the vicinity of an interface between the P-type body region 405 and the gate insulating film 407, and a current flows between the N+-type source region 409 and the drain electrode 415.
In the steps of manufacturing the semiconductor device 401, a silicon oxide film is formed on the surface of the N−-type epitaxial layer 403 including the inner surface of the trench 406. Then, the gate electrode 408 made of doped polysilicon is formed on the silicon oxide film in the trench 406. Thereafter HF (hydrofluoric acid) is supplied to the surface of the portion of the silicon oxide film located outside the trench 406 to remove this portion of the silicon oxide film, in advance of ion implantation for forming the N+-type source region 409.
At this time, the upper portion of the silicon oxide film in the trench 406, i.e., the upper end portion of the gate insulating film 407 is also removed with HF, to result in a portion where the gate electrode 408 and the N+-type source region 409 are opposed to each other without through the gate insulating film 407, as shown in FIG. 9. In the ion implantation for forming the N+-type source region 409, impurity ions may be implanted into not only the N−-type epitaxial layer 403 but also the gate insulating film 407, to denature the film quality of the portion into which the impurity is implanted. Thus, the conventional semiconductor device 401 disadvantageously has a low withstand voltage (gate-to-source withstand voltage) between the gate electrode 408 and the N+-type source region 409.